Eureka Unveils Efficient Training for On-Chip Optical Processors

A new publication from Opto-Electronic Advances; DOI 10.29026/oea.2024.230182 , discusses efficient stochastic parallel gradient descent training for on-chip optical processors.

With the explosive growth of global data volume, space-division multiplexing (SDM) technology has been emerged as a promising solution to enhance the communication capacity. Over the past few decades, SDM has been realized in few-mode fibers, multi-core fiber and free-space optical communication systems. However, all of above solutions face challenges of signal crosstalk because of the mixing between different channels during the transmission of optical signals, resulting in a degradation in signal quality at the receiver. Therefore, digital signal processing (DSP) is necessitated for descrambling. Unfortunately, high-speed DSP chips in the electrical domain are highly complicated, difficult to design, and high power consumption. In recent years, integrated reconfigurable optical processors have been exploited to undo the channel mixing in the optical domain. However, the gradient descent algorithms need to update variables one by one to calculate the loss function with each iteration, which leads to a large amount of computation and a long training time. What's more, the swarm intelligence algorithms such as genetic algorithm (GA) and particle swarm optimization (PSO) algorithm have a large enough population size to ensure the reliability of the training results, which also bring a large amount of computation. Therefore, it is of great significance to find an efficient optimization algorithm suitable for optical matrix configuration for online training of large-scale photonic computing chips and multi-dimensional optical communication systems.

Progress in the online training of optical matrix computing chips has been made; compared to the discrete gradient descent algorithm, GA and PSO algorithm, this method greatly reduces the number of operations, which can greatly save the power consumption in the training process, and is expected to be applied to the online training of ultra-large-scale optical matrix computing chips.

In order to verify the feasibility of the proposed optimization method, the authors designed and fabricated a 6×6 reconfigurable optical processor chip based on cascaded Mach-Zehnder Interferometers (MZIs) and carried out online training experiments, including optical switching matrix and optical signal descrambling matrix. Figure 2 shows the application scenario of an optical processor in the MDM optical communication system and the internal structure of the processor. Figure 2 shows the training results, and it can be seen that the training effect is relatively good for the optical switching and optical signal descrambling tasks in the multi-dimensional optical communication system.

On this basis, this reconfigurable optical processor chip to high-speed optical communication systems was used to compensate for crosstalk caused by mode mixing during transmission. Figure 3 shows the experimental setup and obtained results. It can be seen that the quality of the signal is significantly improved when the light passes through the trained photonic chip, as shown in Figs. 3(e) and 3(f), and the bit error rate (BER) is greatly reduced.

Finally, the computational effort of the SPGD algorithm was compared with the traditional gradient algorithm, GA and PSO algorithm when the optical matrix scale is expanded to 10×10, 16×16, 32×32. The results show that the increase of the computational cost of SPGD algorithm is less than that of other algorithms.

Table 1 Comparison of different algorithms

Keywords: optical communications / optical signal processing / channel descrambling / optical neural network chip / silicon photonics