Seoul National University's College of Engineering announced that a research team led by Professor Chul-Ho Lee from the Department of Electrical and Computer Engineering has outlined a comprehensive roadmap for the 'gate stack'* engineering, a core technology for two-dimensional (2D) transistors, which are attracting attention as next-generation semiconductor devices.
*Gate stack: A layered structure composed of dielectric and metal materials placed above the conductive channel in a transistor, used to electrostatically modulate channel conductance.
The study was published in the highly authoritative international journal Nature Electronics (Impact Factor: 40.9), a leader in semiconductor technology advancement, on September 11.
Most contemporary semiconductors rely on silicon-based Complementary Metal-Oxide-Semiconductor (CMOS) technology. This technology has driven improvements in performance and integration density over the past several decades. As the technology nodes enter the sub-nanometer (nm) regime, however, further scaling is increasingly constrained by physical and electrostatic limits. Two-dimensional (2D) semiconductors have therefore attracted growing attention as beyond-silicon channel materials, as they can maintain their electrical properties even at atomic thickness.
Notably, leading global semiconductor companies and research institutes—including Samsung, TSMC, Intel, and IMEC—have already incorporated plans to adopt 2D semiconductor transistors as the next-generation technology into their technology roadmaps for the post-silicon era (after the mid-2030s) and have launched substantial R&D programs. Thus, 2D semiconductors are shifting from a long-term prospect to a rapidly emerging next-generation core technology for the global semiconductor industry.
However, the most significant obstacle to commercializing 2D semiconductors today is the 'gate stack' integration technology. As the core structure that electrostatically controls channel conduction, gate stack quality determines the device performance and stability. However, directly applying existing silicon transistor processes to 2D semiconductors not only degrades the quality of the dielectric* but also causes issues like defects at the interface and leakage current. Developing new materials and process integrations tailored to 2D interfaces is considered the most critical task for commercializing 2D semiconductors.
*Dielectric: An insulating material that prevents electric current from flowing.
Professor Lee's research team analyzed various gate stack integration methods and quantitatively benchmarked them against performance metrics, thereby outlining future technological development directions.
First, the research categorizes gate stack integration approaches into five categories: (1) van der Waals (vdW) dielectrics, (2) vdW-oxidized dielectrics, (3) quasi-vdW dielectrics, (4) vdW-seeded dielectrics, and (5) non-vdW-seeded dielectrics. Each method was evaluated against metrics such as interface trap density, equivalent oxide thickness, gate leakage density, threshold voltage, and supply voltage. The team benchmarked these metrics against the goals outlined in the International Roadmap for Devices and Systems (IRDS). This process yielded a systematic development roadmap that serves as a reference for both academia and industry.
The research team also demonstrated the potential for gate stacks incorporating ferroelectric* materials to be scaled up into next-generation devices. For instance, utilizing ferroelectric-embedded gate stacks enables the realization of ultra-low-power logic, non-volatile memory, and in-memory computing. Furthermore, the researchers specifically outlined practical requirements, including Back-End-of-Line (BEOL) compatibility, low-temperature deposition (< 400°C), wafer-scale uniformity, and long-term reliability. This emphasizes real-world industrial applicability beyond theoretical discussion.
*Ferroelectric: A material that retains remanent polarization even without an external electric field, useful for non-volatile memory.
This research holds significant meaning as it quantitatively compares the performance of 2D semiconductor gate stacks using various metrics and evaluates them in relation to IRDS targets, thereby providing a blueprint for next-generation semiconductor development. It not only confirmed the feasibility of ultra-low-power, high-performance transistors but also innovatively proposed specific technical directions considering future monolithic 3D integration and BEOL-compatible processes. Furthermore, the technologies presented in this study are expected to become core foundational technologies driving the advancement of next-generation ICT infrastructure, such as AI semiconductors, ultra-low-power mobile chips, and ultra-high-density servers.
Professor Lee stated, "The biggest obstacle to commercializing 2D transistors is the implementation of high-quality gate stacks. This research presents a standard blueprint to overcome this challenge, making it highly impactful both academically and industrially. We plan to actively expand research on device-level integration and commercialization through industry-academia collaboration."
Professor Chul-Ho Lee's research team at SNU is actively leading international academia in the field of 2D semiconductor devices, particularly high-quality gate stack engineering. They are recognized as a leading group driving global trends in future semiconductor research, not only proposing concepts but also conducting broad research encompassing device-level fabrication and process integration, and spearheading solutions to core challenges in next-generation semiconductors.
Dr. Yeon Ho Kim, the first author of this paper, is currently working as a postdoctoral researcher at Seoul National University's Department of Electrical and Computer Engineering, conducting research on contact and gate stack engineering for two-dimensional transistors. Based on this research achievement, he is expected to demonstrate academic and industrial leadership in the field of next-generation 2D semiconductor integrated devices.
This research was supported by the Ministry of Science and ICT under the Next-Generation Intelligent Semiconductor Technology Development Project and the Nano and Material Technology Development Program (Future Technology Labs). The graduate researchers received additional support from BK21 Four and the SNU Graduate School of AI Semiconductor.
□ Introduction to the SNU College of Engineering
Seoul National University (SNU) founded in 1946 is the first national university in South Korea. The College of Engineering at SNU has worked tirelessly to achieve its goal of 'fostering leaders for global industry and society.' In 12 departments, 323 internationally recognized full-time professors lead the development of cutting-edge technology in South Korea and serving as a driving force for international development.
