As AI systems become more advanced, memory is required to transfer larger amounts of data at higher speeds. But conventional planar semiconductor scaling is running out of room. A KAIST research team has now addressed a key weakness in three-dimensional, vertically stacked memory devices, opening a new path to faster, more power-efficient AI semiconductors.
KAIST (President Choongsik Bae) announced on August 25 that a research team led by Professor Jimin Kwon from the School of Electrical Engineering has developed a new multilayer interlayer dielectric structure that reduces defects and significantly enhances the performance of oxide vertical channel transistors (VCTs), a next-generation memory device. The study was conducted in collaboration with researchers from UNIST, Yonsei University, and other Korean institutions.
DRAM, which serves as the main memory in computers, has advanced over the past several decades by scaling down device size while reducing power leakage. More recently, vertical channel structures, in which current flows vertically, have become a key technology for increasing memory density.
The challenge is oxygen vacancies — defects caused by the absence of oxygen atoms in the oxide semiconductor — which destabilizes the material's electrical properties. But oxygen cannot simply be supplied without limit: when oxygen is supplied to suppress oxygen vacancies, some of the oxygen tends to migrate further, reaching the metal electrode and oxidizing it, which degrades device performance instead. The channel needed oxygen; the electrode did not. Therefore, selectively controlling oxygen flow became a key challenge.
The KAIST team developed a new multilayer interlayer dielectric consisting of silicon nitride/silicon dioxide/silicon nitride (SiN/SiO₂/SiN), engineered to function as an "oxygen tunnel" that steers oxygen selectively toward the channel while blocking its path to the electrode. The structure enabled stable compensation of oxygen vacancies in the oxide semiconductor while simultaneously suppressing unwanted oxidation at the electrode, thereby resolving the trade-off.
As a result, the researchers achieved world-class current density and data retention time in oxide vertical channel transistors.
The device also demonstrated outstanding operational stability. Even after more than ten million cycles of harsh electrical stress testing, the threshold voltage shift remained below 50 millivolts (mV), confirming its high reliability as a memory device.
The team further evaluated system-level performance by integrating conventional silicon CMOS technology with the new oxide semiconductor platform. The results suggest that this approach could significantly improve the performance of next-generation compute-in-memory (CIM) systems, intelligent semiconductors that perform AI computation directly inside memory.
Hyeonho Gu, the first author of the study, said, "This research is significant because it goes beyond improving memory density and addresses the long-standing instability problem in 3D devices through a new approach based on oxygen migration control." He added, "We expect this technology to play a key role in accelerating the commercialization of ultra-low-power, high-performance compute-in-memory systems required for the AI era."
This study was led by KAIST researcher Hyeonho Gu as the first author and was published on May 20 in Advanced Functional Materials, a leading international journal in materials science. The paper was also selected as a Front Cover article in recognition of its academic significance and originality.
※ Paper title: Oxygen-Tunnel Indium Tin Oxide Vertical Channel Transistors with Enhanced Current Density and Reliability for Monolithic 3D Compute-In-Memory Systems
DOI: https://doi.org/10.1002/adfm.202531989
※ Author information: Hyeonho Gu (KAIST, first author); Yongwoo Lee (KAIST, corresponding author); Haksoon Jung (KAIST, corresponding author); Jimin Kwon (KAIST, corresponding author); Hoichang Jeong (UNIST, co-author); Yanfeng Zhao (UNIST, co-author); Heesoo Yang (UNIST, co-author); Minho Park (UNIST, co-author); Hyeonjin Lee (UNIST, co-author); Seunghun Baek (UNIST, co-author); Minju Song (UNIST, co-author); Junghwan Kim (UNIST, co-author); Youngmin Jo (KAIST, co-author); Hyunjin Park (Korea Research Institute of Chemical Technology, co-author); Munhyeon Kim (Seoul National University of Science and Technology, co-author); Jae-Joon Kim (Seoul National University, co-author); Kyuho Jason Lee (Yonsei University, co-author); and Byungjo Kim (UNIST, co-author).
This research was supported by the National Semiconductor Laboratory Program and the Excellent Young Researcher Program of the National Research Foundation of Korea, funded by the Ministry of Science and ICT; the Broadcast and Telecommunications Industry Technology Development Program of the Institute of Information & Communications Technology Planning & Evaluation; and the Super Gap Technology Development Program of the Korea Evaluation Institute of Industrial Technology, funded by the Ministry of Trade, Industry and Energy.
