Research Unveils Ultra-Compact Semiconductor for AI, 6G

Abstract

This work presents an output-capacitor-less digital-assisted analog low-dropout regulator digital-assisted analog LDO (DA-ALDO) that employs a seamless digital-to-analog transfer (D2A-TF) technique enabled by a local ground generator (LGG). The proposed architecture extracts only the strengths of digital LDOs (DLDOs)-fast transient response and low voltage droop-and analog LDOs (ALDOs)-high power supply rejection ratio (PSRR)-to achieve an optimized performance without inheriting their drawbacks. The proposed DA-ALDO is fabricated in a 28-nm CMOS process and achieves a PSRR of −57.6 and −53.7 dB at 10 kHz under load currents of 1 and 100 mA, respectively. It exhibits a voltage droop of only 54mV and a fast settling time of 667 ns in response to a 99-mA load step while consuming a quiescent current of 338.5 μ A. The regulator occupies a compact active area of 0.032 mm2 and achieves a figure of merit (FoM) of 0.029 ps.

A research team, led by Professor Heein Yoon in the Department of Electrical Engineering at UNIST has unveiled a groundbreaking ultra-small hybrid low-dropout regulator (LDO) that promises to revolutionize power management in advanced semiconductor devices. This innovative chip not only stabilizes voltage more effectively, but also filters out noise-all while taking up less space-opening new doors for high-performance system-on-chips (SoCs) used in AI, 6G communications, and beyond.

The new LDO combines analog and digital circuit strengths in a hybrid design, ensuring stable power delivery even during sudden changes in current demand-like when launching a game on your smartphone-and effectively blocking unwanted noise from the power supply.

What sets this development apart is its use of a cutting-edge digital-to-analog transfer (D2A-TF) method and a local ground generator (LGG), which work together to deliver exceptional voltage stability and noise suppression. In tests, it kept voltage ripple to just 54 millivolts during rapid 99 mA current swings and managed to restore the voltage to its proper level in just 667 nanoseconds. Plus, it achieved a power supply rejection ratio (PSRR) of -53.7 dB at 10 kHz with a 100 mA load, meaning it can effectively filter out nearly all noise at that frequency.

Another major advantage is its size-at only 0.032 mm² when made with a 28-nanometer CMOS process-thanks to the elimination of bulky external capacitors. This tiny footprint makes it ideal for highly integrated SoCs, where multiple functions need to be packed into a small space.

Lead researcher Changmin An explained, "Traditional hybrid LDOs often require large capacitors to smooth out digital-to-analog transitions, which can be a bottleneck. Our new design solves this problem with a seamless digital-analog transfer technique, making it both smaller and more efficient."

Designed to activate only when needed during sudden power surges, this LDO also consumes very little standby power. Its overall performance, measured by a comprehensive figure of merit (FoM), is a remarkable 0.029 picoseconds-setting a new global benchmark.

Professor Yoon added, "This ultra-compact, low-power LDO offers outstanding voltage stability and noise reduction, making it highly suitable for next-generation AI chips and 6G communication modules. It's a versatile solution that can be widely adopted across high-performance electronics."

The findings of this research have been published on September 3 in the Journal of Solid-State Circuits, a leading journal in circuit design. The project was supported by the Ministry of Science and ICT (MSIT), the IC Design Education Center (IDEC), and the Institute of Information & Communications Technology Planning & Evaluation (IITP).

Journal Reference

Changmin An, Hyogyoung An, Hyeonjun Nam, and Heein Yoon, "A −53.7-dB PSRR, Fast-Transient Output-Capacitor-Less Digital-Assisted Analog LDO Using Seamless Digital-to-Analog Transfer Technique," IEEE JSSC, (2025).