A few months ago, New York state redesignated Binghamton University's Integrated Electronics Engineering Center as a Center for Advanced Technology, guaranteeing $1 million per year for research over the next decade.
Now, the IEEC has received more key funding: A $1.2 million award from South Korea's National Nano Fabrication Center (NNFC) will help researchers develop the next generation of "2.5D" (2.5-dimensional) electronics packaging. The goal is to better bridge the gap between silicon microchips and the supporting components that make our devices work.
SUNY Distinguished Professor S.B. Park, who serves as IEEC director, said the award reflects Binghamton's "track record of excellence in electronics packaging."
"Electronics packaging is the most important technical subject for the nation and the world," said Park, a faculty member at the Thomas J. Watson College of Engineering and Applied Science's Department of Mechanical Engineering.
"We've been taking advantage of our advancements in electronics - for consumer electronics, high-performance computing, data centers and everything else - that have made things smaller and we can fit more things in a given area of silicon. That's been the focus, and everybody got the benefit out of that. However, that race is almost over, if not already over, because we cannot put more things in a given area anymore."
To explain the difference, he offers an analogy to the human body: "All electronics have two pieces. One is silicon, and the other is packaging. Silicon is the brain, and everything outside of the brain - skin, bones, nerves and blood - is electronics packaging. I speak for electronics packaging and its importance, yet without the brain, we are nobody - they need to work together."
Although microchips and packaging are both important to how a device works, those areas are generally developed separately, functioning together only in the final product. As devices have become smaller over the past 20 years, designers, seemingly, have reached the limit on how tiny the chips can be, and manufacturers have struggled with stacking chips to conserve space.
Park makes another comparison to explain the issue: "In a skyscraper like the Empire State Building, the most important technology is the elevator, to move people up and down effectively. With electronics packaging, we can make that third dimension very effectively, but we cannot effectively remove the heat generated on each 'floor.'"
The idea behind 2.5D electronics packaging is to find a third way between 2D and 3D that can accommodate some chip stacking while also dissipating the heat generated during processing.
Taming the thermodynamics will require new materials, equipment and design concepts. Through this project, the IEEC will work closely with NY CREATES in Albany, which operates a unique fabricating facility for fine-noded 300-milimeter wafers, to complement the needs for packaging and develop workforces for academia and industry.
Park is proud that decision-makers in the electronics industry increasingly look to Binghamton and the IEEC as a top choice for innovation.
"It is not only Korea, but Japan, Taiwan and other leading silicon chipmakers around the world who are recognizing the IEEC as their most effective research partner on packaging," he said. "That is something we can brag about."
