Surpassing Moore’s Law

For decades, improvements in computing power have followed a largely exponential path known as Moore’s Law. As transistors shrink, more of the binary switching elements fit on a computer chip, increasing its computing power. However, the physical limits of transistor chips have slowed this exponential growth and will eventually end Moore’s Law. Soon we will no longer be able to make smaller transistors, forcing chip makers and software developers to come up with new ways to improve speed and efficiency.

To increase computing power, researchers at Pacific Northwest National Laboratory (PNNL) developed a tool, named OpenCGRA, to accelerate the design of new coarse-grained reconfigurable array (CGRA) chip architectures to achieve higher processing performance and efficiency without the benefit of more, smaller transistors.

CGRAs can speed resource-heavy applications such as multimedia or machine learning. The algorithms for these applications are rapidly evolving, so computer architecture must also change along with them. OpenCGRA was designed to help researchers and industry expedite that change.

Computer chip
The end of Moore’s Law will be reached when we can no longer produce smaller transistors to fit more of them on a computer chip. (Composite image by Stephanie King | Pacific Northwest National Laboratory)

From CPUs to CGRAs

CGRAs are hardware accelerators that showcase a design flexibility competitive to current general-purpose processors, commonly called CPUs, yet display high energy efficiency similar to that of application-specific integrated circuits (ASICs). The hardware-software codesign elements of CGRAs have the potential to maximize computing performance with minimal energy input, if designed correctly.

“OpenCGRA helps domain science researchers collaborate with computer scientists to develop potential CGRAs from top-level models to hardware designs,” said PNNL computer scientist Cheng Tan, lead author of the study published in the 2020 IEEE 38th International Conference on Computer Design.

OpenCGRA enables the design and verification of hardware, while the reconfigurability of CGRAs avoids designing ASIC accelerators for all known and unforeseen kernels, therefore eliminating the need for continual reuse of a multi-billion-dollar fabrication facility. By modeling, validating, and evaluating different CGRA models, the software reduces months of hardware design and potentially years of prototyping and fabrication to hours of simulation and evaluation.

While other modeling methods specialize in analyzing a particular aspect of CGRA design, the range of modeling capabilities in OpenCGRA provides users the opportunity to create a CGRA fully optimized to meet their individual needs.

Tahoma computer
OpenCGRA hardware-software codesign can potentially enhance the computing power of high performance computing hardware, such as the one seen here. (Photo by Andrea Starr | Pacific Northwest National Laboratory)

Aligning computational power with national interest

With an ever-increasing rate of technological change occurring globally, the flexibility and efficiency of CGRAs creates the potential for this architecture to become the forefront of chip design. OpenCGRA’s automated solution to reconfiguration during the design process can one day accelerate CGRA development.

“OpenCGRA represents a breakthrough in the push to open hardware design tools to a wider population of computer scientists, putting the power of purpose-designed computing architectures into the hands of users,” said computer scientist Kevin Barker, co-author of the study.

PNNL computer scientists Chenhao Xie, Ang Li, and Antonino Tumeo also contributed to the software development. This research was supported by Laboratory Directed Research and Development funds as part of the Data-Model Convergence Initiative.

OpenCGRA is freely available as an open-sourced software on GitHub.

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