Muir Woods © 2025 EPFL / Paolo Ienne Lopez
Researchers from EPFL, AMD, and the University of Novi Sad have uncovered a long-standing inefficiency in the algorithm that programs millions of reconfigurable chips used worldwide, a discovery that could reshape how future generations of these are designed and programmed.
Many industries, including telecoms, automotive, aerospace and particle physics rely on a special breed of chip called the Field-Programmable Gate Array (FPGA). Unlike traditional chips, FPGAs can be reconfigured almost endlessly, making them invaluable in fast-moving fields where designing a custom chip would take years and cost a fortune. But this flexibility comes with a catch: FPGA efficiency depends heavily on the software used to program them.
Since the late 1990s, an algorithm known as PathFinder has been the backbone of FPGA routing. Its job: connecting thousands of tiny circuit components without creating overlaps. For decades, it worked so well that it became the standard. However, as circuits grew larger, engineers began encountering frustrating slowdowns and occasional outright failures. Designs that should have worked were often labeled "unroutable."
Now, with colleagues from the University of Novi Sad and the technology company AMD, researchers from the Parallel Systems Architecture Laboratory(PARSA) in the School of Computer and Communication Sciences have come one step closer to untangling the inner workings of this classic algorithm.
In their recent paper, which received the Best Paper Award at the 33rd IEEE International Symposium on Field-Programmable Custom Computing Machines, they revealed why these failures happen and how PathFinder's limits can be overcome.
Cracks in the algorithm
"In fact, it's not surprising that PathFinder sometimes fails," explained Shashwat Shrivastava, PhD student with PARSA and first author of the paper. "Very early on, researchers showed that the problem behind FPGA routing is extremely hard. Later, the creators of the original algorithm, together with a few collaborators, found cases where PathFinder would never succeed-but they noted such cases wouldn't appear in practice."
For decades, it seemed they were correct - PathFinder worked surprisingly well.
"PathFinder worked so well, in fact, that when it failed, people rarely questioned the algorithm. Instead of venturing inside to see what was going on, they tweaked its parameters, modified circuits, or switched to larger FPGAs," added Stefan Nikolić, an EPFL alumnus and now a professor at the University of Novi Sad. "Part of the reason for this is that it is rather difficult to understand what PathFinder is actually doing on examples of practical importance. Modern circuits are so large that their signals form veritable on-chip jungles."
Enter the forest
"So, we really needed to look at the individual trees in that jungle," continued Shrivastava, "and I really mean trees. Each signal-a connection that carries information between circuit components-must reach multiple destinations without overlapping other signals. FPGA routing is essentially about building one tree for each signal on the chip."
While working on another project that relied on PathFinder, the team kept seeing results that defied intuition. At first, they blamed external factors, not the algorithm itself. Eventually, they realized they needed controlled examples: small, tricky cases where a solution definitely existed, and in which PathFinder should succeed.
"We needed real, practical examples, and lots of them, to understand what was really going on," Shrivastava explains. "So, we built a framework to automatically extract small, hard problems from real circuits. Watching how PathFinder struggled with these helped us uncover issues that had remained hidden for a very long time."
Power in partnership
"This breakthrough would have been much harder without industry support," said Mirjana Stojilović, Shrivastava's PhD advisor. "From the start, we collaborated with Chirag Ravishankar and Dinesh Gaitonde from AMD. They helped us model FPGAs as close as possible to commercial devices, ensuring our findings had real-world impact."
Once the framework was ready, things moved quickly. The team found that PathFinder often built routing trees larger than necessary, increasing the risk of overlaps. The problem came from the order in which it created and added new branches to the trees.
"In retrospect, this is intuitive, but somehow it went largely unnoticed for many years," Shrivastava said. "Our first solution was simple: try different orders and pick the one that results in the smallest tree. Experimentally, it worked surprisingly well."
Looking ahead
The team is now exploring more scalable solutions. "I am especially proud that Summer@EPFL interns have been contributing significantly. One of them, Sun Tanaka, is also a coauthor of the paper," added Stojilović. "Our discovery could reshape how millions of FPGAs are programmed and influence the design of future generations of these reconfigurable chips."
Read the paper: https://doi.ieeecomputersociety.org/10.1109/FCCM62733.2025.00060
