<(From Left) Ph. D candidate Dae Hyun Kang, Professor Byung Jin Cho>
From smartphones to large-scale AI servers, most digital information in modern society is stored in NAND flash memory*. KAIST researchers have developed an innovative technology that can overcome the limitations of next-generation semiconductors, where more data must be stored in smaller spaces. This advancement is expected to serve as a key enabling technology for realizing ultra-high-capacity memory.
*NAND flash memory: a non-volatile semiconductor memory used in storage devices such as smartphones and SSDs, where data such as photos, videos, and apps are retained even when power is turned off.
KAIST (President Kwang Hyung Lee) announced on the 20th of March that a research team led by Professor Byung Jin Cho of the School of Electrical Engineering has overcome the scaling limitations of 3D V-NAND memory* by implementing a "smart gate" structure that selectively controls electron movement depending on conditions, using a new material applied to an ultra-thin semiconductor layer thinner than a human hair.
*3D V-NAND: a memory technology that stacks memory cells vertically, unlike conventional planar (2D) arrangements, enabling higher data storage density.
This research is particularly significant in that it addresses the longstanding issues of speed degradation and reliability during data write and erase operations by utilizing a novel material called boron oxynitride (BON).
In semiconductor memory, the tunneling layer—a thin insulating layer that acts as a pathway for electrons to move in and out of the memory cell—has historically faced a trade-off between performance and reliability.
With conventional materials, it has been difficult to achieve both simultaneously. For example, the widely used silicon oxynitride (SiON) increases data leakage when the tunneling path is widened to improve erase speed, while narrowing the path to prevent leakage significantly slows down data erasure. This trade-off has been a major obstacle to implementing next-generation penta-level cell (PLC) technology.
PLC technology stores 5 bits of data per memory cell by distinguishing 32 different voltage states, allowing much higher data density within the same physical size.
To overcome this limitation, the research team introduced BON, a completely new material beyond conventional silicon-based systems, into the tunneling layer. This material exhibits a unique physical property in which the energy barrier height differs depending on the type of charge carrier.
Leveraging this property, the team designed an asymmetric energy barrier structure that allows holes (positive charge carriers)—needed for data erase—to pass through easily, while blocking electrons, which represent stored data, from leaking out.
An asymmetric energy barrier refers to a structure in which the energy required for charge carriers to move varies depending on the type of charge. This enables efficient charge transport during erase operations while effectively preventing data loss. The concept is analogous to a "smart gate" that opens easily for entry but firmly blocks exit, implemented at the semiconductor level.
Experimental results showed that devices using the BON tunneling layer achieved up to a 23-fold improvement in erase speed compared to conventional technologies and demonstrated excellent durability with minimal performance degradation even after tens of thousands of operation cycles.
Notably, even under the highly demanding PLC operation—where 32 distinct voltage levels must be precisely controlled—the researchers achieved more than threefold improvement in controlling data distribution across devices.
< Schematic diagram of the asymmetric energy barrier structure and operating principle of the BON tunneling layer >
This achievement is considered by both academia and industry to be beyond a purely experimental result, reaching a level immediately applicable to real semiconductor manufacturing processes.
Professor Byung Jin Cho stated, "This research presents a novel technology that can be directly applied to the production of next-generation ultra-high-capacity memory," adding, "It will significantly contribute to maintaining Korea's technological leadership in the semiconductor industry."
This study was implemented by Dae Hyun Kang, an integrated master's–PhD student in Electrical Engineering, as the first author. The research was presented at the IEEE International Electron Devices Meeting (IEDM) on December 9, one of the most prestigious conferences in the semiconductor field, attracting global attention.
The work also received the Grand Prize (first place overall in the university category) at the 32nd Samsung Human Tech Paper Awards, marking a notable achievement as a traditional semiconductor device study in a competition typically dominated by AI-related research.
※ Paper title: "Bandgap-Engineered Boron Oxynitride Tunneling Layer for Reliable PLC Operation of 3D V-NAND Flash Memory Devices," DOI: https://doi.org/10.1109/IEDM50572.2025.11353681
This research was supported by the National Semiconductor Research Lab Core Technology Development Program funded by the Ministry of Science and ICT.
