A breakthrough has been made toward overcoming both the speed and endurance limitations of low-power memory.
A research team led by Professor Min Hyuk Park of the Department of Materials Science and Engineering at Seoul National University College of Engineering has developed a ferroelectric capacitor that operates rapidly at a voltage as low as 0.6 V and can still distinguish between information states without electrical breakdown after one trillion switching cycles.
The achievement is significant because it offers a solution to a longstanding challenge in ferroelectric memory: the difficulty of achieving both fast operation and long device lifetime. By precisely engineering the interface between the electrode and the ferroelectric material, the researchers simultaneously achieved a low operating voltage, rapid polarization switching, and high cycling stability. Based on these results, they also demonstrated the potential for the technology to be used in next-generation low-power memory with a structure similar to DRAM.
The research was conducted jointly with researchers from Hanyang University, Pohang Accelerator Laboratory, and Samsung Electronics, and the findings were published in the internationally renowned journal Nature Communications.
As the volume of data processed by AI servers and mobile devices continues to grow, technologies that can simultaneously improve memory performance and power efficiency are becoming increasingly important. Power efficiency is a particularly critical challenge in both high-bandwidth memory (HBM) used in AI servers and LPDDR, a low-power DRAM standard used in smartphones and other mobile devices.
DRAM is a widely used form of high-speed volatile memory found in computers, smartphones, and AI servers. It stores information by holding electrical charge in capacitors, but because the charge leaks away over time, it must be periodically replenished to retain information. This "refresh" process affects both the power consumption and operating efficiency of memory.
Ferroelectric memory, by contrast, stores information using "polarization," the electrical orientation within a material. The two polarization directions correspond to the digital states "0" and "1." By taking advantage of its nonvolatile characteristics based on remanent polarization, in which polarization remains even after the external electric field is removed, ferroelectric memory can reduce the power burden associated with periodic refresh. Ferroelectrics were also identified as promising materials for next-generation semiconductors in the "Semiconductor Future Technology Roadmap" announced by Korea's Ministry of Science and ICT in 2023.
The hafnia-zirconia (HZO) used in this research is a ferroelectric material combining hafnium oxide and zirconium oxide. Both oxides have already been used in semiconductor mass production: hafnium oxide as a gate dielectric that helps control current in transistors, and zirconium oxide as a capacitor dielectric for storing charge in DRAM. HZO offers the advantages of high compatibility with existing semiconductor manufacturing processes and the ability to form uniform thin films only a few nanometers thick using atomic layer deposition.
However, for HZO to be used in next-generation DRAM-class memory, low voltage, fast operation, and long lifetime must all be achieved simultaneously. Writing information to ferroelectric memory requires switching the direction of polarization, and faster polarization switching generally requires a higher voltage. Higher voltages, however, place greater stress on the device and can shorten its cycling lifetime. This difficulty in simultaneously improving operating speed and cycling endurance is known as the "speed–endurance dilemma."
Simply reducing the thickness of the thin film also has limitations as a means of lowering the operating voltage. As the film becomes extremely thin, the electric field required for polarization switching and the influence of the electrode interface become increasingly significant, making it difficult to sufficiently reduce the operating voltage through thickness reduction alone.
To address this challenge, the research team focused on engineering the interface between the electrode and the ferroelectric material. Using atomic layer deposition, the researchers controlled the crystallographic orientation and surface properties of the titanium nitride (TiN) electrode and suppressed interfacial oxidation to form a thin and uniform interfacial layer. This reduced voltage loss at the interface and created conditions that allowed polarization to switch uniformly.
As a result, the researchers achieved polarization switching at a low voltage of 0.6 V in a 5-nm-thick HZO capacitor. Even at this low voltage, the device produced a clear polarization signal sufficient to distinguish between different information states.
In the test device, the time required to switch half of the total polarization was approximately 40 ns at 0.6 V and approximately 8 ns at 1 V. A nanosecond (ns) is one billionth of a second. Under both voltage conditions, no hard electrical breakdown was observed even after one trillion switching cycles, and the two polarization states remained distinguishable. When cycling endurance was evaluated using a criterion of less than 20% polarization loss, the device endured 600 billion cycles at 0.6 V and one trillion cycles at 1 V. The researchers explained that, compared with previously reported ferroelectric capacitors, the device achieved a world-leading combination of operating voltage, switching speed, and endurance. The peer-reviewed paper reports corresponding measured switching values of 42.1 ns at 0.6 V and 8.1 ns at 1.0 V.
The team attributed this performance to the reduction in voltage loss through electrode and interface engineering and the use of the electric field inside the device to assist polarization switching. In general, the "depolarization field" within a ferroelectric can weaken remanent polarization and therefore adversely affect information retention. The researchers found, however, that during the initial stage when the polarization begins to reverse direction, this field can help reduce the external voltage required for polarization switching.
Using a model that incorporates the properties of the electrode and interface, the researchers explained this mechanism and proposed a design strategy for obtaining a sufficient polarization signal at low voltage even in thin ferroelectric films. They also found that polarization switching tended to become faster as the device area decreased. Based on their measurements, they predicted that even smaller, nanometer-scale devices could achieve nanosecond-scale polarization switching at low voltages. This demonstrates the potential for operation at DRAM-class speeds. The paper further projects sub-nanosecond polarization reversal at DRAM-relevant capacitor dimensions.
The research team also explored ways to incorporate these characteristics into a memory architecture. Based on the "1T–1C" structure, which consists of one transistor and one capacitor like DRAM, the researchers proposed "common-plate ferroelectric memory (CP-FeRAM)," which uses remanent polarization to store and read information. In this architecture, the voltage of an electrode shared by multiple memory cells is maintained at a constant level.
Computer simulations of circuit operation based on experimentally measured polarization characteristics showed that information could potentially remain distinguishable using remanent polarization even after the stored charge had decreased. A test capacitor array sharing a common electrode also showed uniform device operation, with no significant polarization loss observed even after repeated cycling of neighboring devices.
The significance of the research lies in simultaneously achieving low operating voltage, rapid polarization switching, and high endurance, and connecting these characteristics to a DRAM-like memory architecture. Information storage based on remanent polarization could provide a foundation for next-generation memory that reduces the burden of periodically replenishing charge through refresh.
The technology is also expected to offer advantages for high-density memory integration. As memory cells become smaller, the electrical signals used to distinguish stored information also decrease, making the information more difficult to read. By utilizing large remanent polarization, it may be possible to maintain a sufficient readout signal even as capacitor size decreases, helping to fit more memory cells into the same area.
The researchers expect that HZO's compatibility with materials and processes already used in the semiconductor industry, combined with the low-voltage, high-speed, and high-endurance characteristics demonstrated in this study, will broaden the potential for industrial applications of ferroelectric memory. They also expect that the design and operating principles presented in the study could be applied not only to highly integrated DRAM-class memory but also to the development of low-power embedded memory integrated alongside computing circuitry.
Professor Park, who supervised the research, said, "Creating memory that operates rapidly at low voltage while also withstanding repeated use over a long period is an important challenge." He added, "This study is significant because electrode and interface engineering enabled us to achieve all three characteristics together and offer a solution to the longstanding tradeoff between speed and lifetime in ferroelectric memory."
He continued, "HZO is a promising ferroelectric that can be developed using oxide materials and process technologies already established in the semiconductor industry." He added, "We expect the interface design and polarization-switching principles presented in this study to contribute to advances in low-power, high-density memory technologies."
The paper's first author, Dr. Geun Hyeong Park, earned his Ph.D. in Materials Science and Engineering through Seoul National University's integrated M.S./Ph.D. program and is currently a postdoctoral researcher at the Inter-University Semiconductor Research Center at Seoul National University. Building on his experience in memory-device architecture design and analysis of operating characteristics, he plans to continue developing low-power, high-performance memory devices aimed at improving the power efficiency and integration density of AI semiconductors.
The research was supported by the Ministry of Science and ICT, the National Research Foundation of Korea, and Samsung Electronics.
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