A physics-guided AI framework automatically optimizes 2.4 GHz CMOS low-noise amplifiers, reducing power consumption by 62% and improving linearity by 10.7 dB compared with an expert-designed baseline, while nearly doubling the rate of successful circuit simulations under foundry design constraints.
Every smartphone, Wi-Fi router and wearable device relies on a tiny circuit called a low-noise amplifier (LNA) to extract faint radio signals out of the air without drowning them in noise. Designing one is a delicate balancing act: power consumption, noise and signal fidelity pull against each other, and a skilled engineer typically spends days of iterative simulation and hand-tuning to get it right.
Automating that job has proven surprisingly hard for artificial intelligence. Chip designs must obey the strict rules of a foundry's process design kit (PDK). For example, on-chip inductors can only be chosen from a fixed library of pre-characterized components and most randomly generated candidate circuits simply fail. In the team's preliminary experiments, more than half of the simulated designs were invalid, violating transistor operating regions or impedance-matching requirements before the optimization could even get started.
Researchers from the Singapore University of Technology and Design, Tianjin University and Henan University of Technology now report a way around this bottleneck: teach the algorithm some physics before letting it search. Much like handing a student the textbook before the exam, their framework first uses simple resonance and impedance-matching relationships to generate "warm-start" designs that are physically sensible and buildable from the foundry's component library. A validity gate then screens every simulated candidate, so that only physically meaningful results are used to train the artificial intelligence (AI) model that steers optimization toward the best power–noise–linearity trade-offs.
The payoff is striking. Optimizing a 2.4 GHz LNA in a commercial 40 nm CMOS process with a budget of just 190 circuit simulations, roughly 16–19 hours of computing, versus days of manual iteration. The framework cut power consumption from 14.1 mW to 5.4 mW, a 62% reduction, while improving linearity (IIP3) by 10.7 dB compared with a handcrafted expert design, at the cost of a modest 0.21 dB noise-figure penalty. The share of valid simulations jumped from 47.5% during unguided sampling to 95.7% under guided optimization, roughly twice the rate achieved by popular open-source optimizers under the same budget.
To show the recipe is not a one-off, the team applied the identical pipeline to a structurally different amplifier. Without retuning the algorithm, it again outperformed the expert baseline, reducing power by 25%, lowering the noise figure by 0.36 dB and improving linearity by 2.59 dB.
The authors note that the study is a schematic-level proof of concept; future work will extend the framework to layout-extracted designs, process–voltage–temperature corners and other RF blocks such as power amplifiers, mixers and oscillators. Ultimately, the approach points toward practical, physics-aware AI design assistants for the analog circuits that connect our devices to the world.
This paper "Physics-guided multi-objective Bayesian optimization for process-aware CMOS LNA design" was published in Interdiscipline.
Jayarajan J, Ji S, Thangarasu B, Mahalingam N, Miao B, et al. Physics-guided multi-objective Bayesian optimization for process-aware CMOS LNA design. Interdiscipline 2026(1):0002, https://doi.org/10.55092/interdiscipline20260002.
