A new dimension in optical computing
Convolutional neural networks (CNNs) rely heavily on matrix–vector multiplication (MVM), but most existing photonic MVM chips use only one or two optical degrees of freedom (DoFs), limiting their parallelism and flexibility. Now, a team led by Prof. Daoxin Dai and Prof. Yiwei Xie at Zhejiang University (China) has developed the first photonic architecture that simultaneously harnesses three fundamental DoFs of light: wavelength, mode, and polarization.
192 channels, one chip
The integrated silicon photonic chip combines thirty‑two wavelength channels, three guided spatial modes (TE₀, TE₁, TE₂ and their TM counterparts), and dual polarizations, yielding a total of 192 parallel computing channels. This is achieved by a six‑channel hybrid mode/polarization (de)multiplexer and a 6×32 array of elliptically shaped microring resonators (EMRs) that independently weight each channel. The EMRs exhibit low loss (1‑2 dB) and an extinction ratio of ~20 dB under a low tuning voltage (1 V).
Large, reconfigurable convolution kernels
Unlike conventional electronic "small‑yet‑deep" strategies (e.g., stacking 3×3 kernels), the photonic chip natively supports large and dynamically adjustable kernels up to 13×13. By selectively combining different wavelength, mode, and polarization channels, the same hardware can perform 3×3, 5×5, 7×7, or even 13×13 convolutions without physical reconfiguration. Experiments on image edge detection and mean filtering show that larger kernels capture global structural contours while smaller kernels preserve fine details – a flexibility that is difficult to achieve with traditional small‑kernel photonic accelerators.
Denoising proves the advantage
The team tested the chip on image denoising using a small convolutional encoder‑decoder network. Under Gaussian noise, a 3×3 kernel gave the best peak signal‑to‑noise ratio (PSNR 20.20 dB); under structured stripe noise, the 7×7 kernel performed best (PSNR 16.67 dB). These results confirm that multi‑scale kernel reconfigurability is essential for adapting to different noise characteristics – a capability directly enabled by the chip's 192‑dimensional multiplexing.
Record throughput and scalability
Operating at 40 Gbaud modulation, the chip achieves a measured throughput of 15.36 tera‑operations per second (TOPS), calculated as 2 (polarizations) × 6 (modes) × 32 (wavelengths) × 40 Gbaud. The throughput can be further increased by adopting higher‑speed modulators or adding more optical channels. The architecture is fully compatible with standard silicon photonics fabrication.
Outlook
This work demonstrates for the first time that wavelength, mode, and polarization can be simultaneously harnessed for highly parallel on‑chip optical computing. The team notes that future efforts will focus on integrating on‑chip nonlinear activation functions and co‑optimized photonic‑electronic training algorithms. The proposed chip offers a promising path toward low‑latency, energy‑efficient optical processors for edge computing, real‑time vision, and next‑generation AI systems that demand high‑precision visual processing.
Funding
The research was supported by the National Natural Science Foundation of China, the Ministry of Education of China, the Fundamental Research Funds for the Central Universities, and the Leading Innovative and Entrepreneur Team Introduction Program of Zhejiang.
